Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
346
22.4.4.3 Ending Multi-buffer Transfers
All multi-buffer transfers must end as shown in Row 1 of Table 22-4 on page 345. At the end of every buffer
transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer
transferred was the last buffer and the DMAC transfer is terminated.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in
memory so that LLI.DMAC_CTRLBx.SRC_DSCR is set to 0.
22.4.5 Programming a Channel
Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be
programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is
used. The different transfer types are shown in Table 22-4 on page 345.
The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx,
DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are
enabled.
22.4.5.1 Programming Examples
Single-buffer Transfer (Row 1)
1. Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled)
channel.
2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status
register, DMAC_EBCISR.
3. Program the following channel registers:
a. Write the starting source address in the DMAC_SADDRx register for channel x.
b. Write the starting destination address in the DMAC_DADDRx register for channel x.
c. Write the next descriptor address in the DMA_DSCRx register for channel x with 0x0..
d. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1 as shown in Table
22-4 on page 345.
e. Write the control information for the DMAC transfer in the DMAC_CTRLAx and
DMAC_CTRLBx reg-
isters for channel x. For example, in the register, you can program the following:
 i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow
control device by programming the FC of the DMAC_CTRLBx register.
 ii. Set up the transfer characteristics, such as:
–Transfer width for the source in the SRC_WIDTH field.
–Transfer width for the destination in the DST_WIDTH field.
– Incrementing/decrementing or fixed address for source in SRC_INC field.
– Incrementing/decrementing or fixed address for destination in DST_INC field.
f. Write the channel configuration information into the DMAC_CFGx register for channel x.
 i. Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking
interface to handle source/destination requests. Writing a ‘0’ activates the software handshaking
interface to handle source/destination requests.
 ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a
handshaking interface to the source and destination peripheral. This requires programming the
SRC_PER and DST_PER bits, respectively.