Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
344
When the peripheral is not the flow controller, then the last transaction register DMAC_LAST is not used, and the
values in these registers are ignored.
Chunk Transactions
Writing a 1 to the DMAC_CREQ[2x] register starts a source chunk transaction request, where x is the channel
number. Writing a 1 to the DMAC_CREQ[2x+1] register starts a destination chunk transfer request, where x is the
channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_CREQ[2x] or DMAC_CREQ[2x+1].
Single Transactions
Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x is the channel
number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single transfer request, where x is the
channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or DMAC_SREQ[2x+1].
The software can poll the relevant channel bit in the DMAC_CREQ[2x]/DMAC_CREQ[2x+1] and
DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested chunk or single
transaction has completed.
22.4.4 DMAC Transfer Types
A DMAC transfer may consist of single or multi-buffer transfers. On successive buffers of a multi-buffer transfer,
the DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following
methods:
 Buffer chaining using linked lists
 Contiguous address between buffers
On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx registers in the DMAC
are re-programmed using either of the following methods:
 Buffer chaining using linked lists
When buffer chaining using linked lists is the multi-buffer method of choice, and on successive buffers, the
DMAC_DSCRx register in the DMAC is re-programmed using the following method:
 Buffer chaining using linked lists
A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC
to set up and describe the buffer transfer.
22.4.4.1 Multi-buffer Transfers
Buffer Chaining Using Linked Lists
In this case, the DMAC re-programs the channel registers prior to the start of each buffer by fetching the buffer
descriptor for that buffer from system memory. This is known as an LLI update.
DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that stores the address
in memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor
(DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx).
To set up buffer chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx registers are
fetched from system memory on an LLI update. The updated content of the DMAC_CTRLAx register is written
back to memory on buffer completion. Figure 22-4 on page 345 shows how to use chained linked lists in memory
to define multi-buffer transfers using buffer chaining.