Datasheet

343
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
Single-buffer DMAC transfer: Consists of a single buffer.
Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC
transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and
contiguous buffers. The source and destination can independently select which method to use.
 Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory
where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer
(buffer descriptor) and a descriptor pointer register. The DMAC fetches the LLI at the beginning of
every buffer when buffer chaining is enabled.
 Contiguous buffers – Where the address of the next buffer is selected to be a continuation from the
end of the previous buffer.
Channel locking: Software can program a channel to keep the AHB master interface by locking the arbitration for
the master bus interface for the duration of a DMAC transfer, buffer, or chunk.
Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the
duration of a DMAC transfer, buffer, or transaction (single or chunk). Channel locking is asserted for the duration of
bus locking at a minimum.
22.4.2 Memory Peripherals
Figure 22-3 on page 342 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no
handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once
the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative
to not having a transaction-level handshaking interface is to allow the DMAC to attempt AMBA transfers to the
peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait
states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus.
By using the handshaking interface, the peripheral can signal to the DMAC that it is ready to transmit/receive data,
and then the DMAC can access the peripheral without the peripheral inserting wait states onto the bus.
22.4.3 Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or chunk transfers. The
operation of the handshaking interface is different and depends on whether the peripheral or the DMAC is the flow
controller.
The peripheral uses the handshaking interface to indicate to the DMAC that it is ready to transfer/accept data over
the AMBA bus. A non-memory peripheral can request a DMAC transfer through the DMAC using one of two
handshaking interfaces:
 Hardware handshaking
 Software handshaking
Software selects between the hardware or software handshaking interface on a per-channel basis. Software
handshaking is accomplished through memory-mapped registers, while hardware handshaking is accomplished
using a dedicated handshaking interface.
22.4.3.1 Software Handshaking
When the slave peripheral requires the DMAC to perform a DMAC transaction, it communicates this request by
sending an interrupt to the CPU or interrupt controller.
The interrupt service routine then uses the software registers to initiate and control a DMAC transaction. These
software registers are used to implement the software handshaking interface.
The SRC_H2SEL/DST_H2SEL bit in the DMAC_CFGx channel configuration register must be set to zero to
enable software handshaking.