Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
338
22. AHB DMA Controller (DMAC)
22.1 Description
The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to
a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair.
In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads
the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data
transfer. This is also known as a dual-access transfer.
The DMAC is programmed via the APB interface.
The DMAC embeds 6 channels:
22.2 Embedded Characteristics
 Programmable Arbitration Policy, Modified Round Robin and Fixed Priority are Available
 Acting as one Matrix Master
 Embeds 4 (SAM3A and 100-pin SAM3X) or 6 (144-pin SAM3X and 217-pin SAM3X8H
(1)
) channels
Note: 1.This device is not commercially available. Mounted only on the SAM3X-EK evaluation kit.
 Linked List support with Status Write Back operation at End of Transfer
 Word, HalfWord, Byte transfer support.
 Handles high speed transfer of SPI0-1, SSC and HSMCI (peripheral to memory, memory to peripheral)
 Memory to memory transfer
DMAC Channel Number FIFO Size
08
18
28
332
48
532
Table 22-1. DMA Channels
DMA Channel Size
SAM3A
100-pin SAM3X
144-pin SAM3X
217-pin SAM3X8H
(1)
8 bytes FIFO for Channel Buffering
3
(Channels 0, 1 and 2)
4
(Channels 0, 1, 2 and 4)
32 bytes FIFO for Channel Buffering
1
(Channel 3)
2
(Channels 3 and 5)