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SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
21.8.2 Bus Matrix Slave Configuration Registers
Name: MATRIX_SCFG0..MATRIX_SCFG8
Address: 0x400E0440
Access: Read-write
This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
• SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reach for a burst it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slave by when very long burst are used.
This limit should not be very small though. Unreasonable small value will break every burst and Bus Matrix will spend its
time to arbitrate without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
• DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in having a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of current slave access, if no other master request is pending, the slave stay connected with the last master
having accessed it.
This results in not having the one cycle latency when the last master re-tries access on the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master which
number has been written in the FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master re-tries access on the slave again.
• FIXED_DEFMSTR: Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a
master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0.
31 30 29 28 27 26 25 24
–––––– ARBT
23 22 21 20 19 18 17 16
– – – FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
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SLOT_CYCLE