Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
330
21.8.1 Bus Matrix Master Configuration Registers
Name: MATRIX_MCFG0..MATRIX_MCFG5
Address: 0x400E0400
Access: Read-write
This register can only be written if the WPEN bit is cleared in the “Write Protect Mode Register” .
• ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single access allowing rearbitration at each beat of the INCR
burst.
2: Four Beat Burst
The undefined length burst is split into 4 beats burst allowing rearbitration at each 4 beats burst end.
3: Eight Beat Burst
The undefined length burst is split into 8 beats burst allowing rearbitration at each 8 beats burst end.
4: Sixteen Beat Burst
The undefined length burst is split into 16 beats burst allowing rearbitration at each 16 beats burst end.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
––––– ULBT