Datasheet
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
324
21.2.3 Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense, for example
allowing access from the USB High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or
simply not wired, and shown as “-” in the following table.
21.3 Memory Mapping
Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several
memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e. internal ROM or internal Flash) becomes
possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that allows to perform
remap action for every master independently.
21.4 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
some masters. This mechanism allows to reduce latency at first accesses of a burst or single transfer. The bus
granting mechanism allows to set a default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters: no default master, last access
master and fixed default master.
21.4.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No
Default Master suits low power mode.
21.4.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to the last master that
performed an access request.
Table 21-3. SAM3A/X series Master to Slave Access
Masters 0 1 2 3 4 5
Slaves
Cortex-M3
I/D Bus
Cortex-M3 S
Bus PDC
USB High
Speed DMA
DMA
Controller
EMAC
DMA
0 Internal SRAM0 - X X X X X
1 Internal SRAM1 - X X X X X
2 Internal ROM X - X X X X
3 Internal Flash X - - - - -
4 USB High Speed Dual Port RAM - X - - X -
5 Nand Flash Controller RAM - X X X X X
6 External Bus Interface - X X X X X
7 High Speed Peripheral Bridge - X X - X -
8 Low Speed Peripheral Bridge - X - - X -