Datasheet

323
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
21. Bus Matrix (MATRIX)
21.1 Description
Bus Matrix implements a multi-layer AHB, based on AHB-Lite protocol, that enables parallel access paths between
multiple AHB masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 6
AHB Masters to
9 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the
default master of the accessed slave which is connected directly (zero cycle latency).
The Bus Matrix user interface is compliant with
the ARM Advance Peripheral Bus (APB) and provides a Chip
Configuration User Interface with Registers that allow the Bus Matrix to support application specific features.
21.2 Embedded Characteristics
21.2.1 Matrix Masters
The Bus Matrix of the SAM3A/X series product manages 5 (SAM3A) or 6
(SAM3X) masters, which means that
each master can perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing,
all the masters have the same decoding.
21.2.2 Matrix Slaves
The Bus Matrix of the SAM3A/X series product manages 9 slaves. Each slave has its own arbiter, allowing a
different arbitration per slave.
Table 21-1. List of Bus Matrix Masters
Master 0 Cortex-M3 Instruction/Data
Master 1 Cortex-M3 System
Master 2 Peripheral DMA Controller (PDC)
Master 3 USB OTG High Speed DMA
Master 4 DMA Controller
Master 5 Ethernet MAC (AT91SAM3X)
Table 21-2. List of Bus Matrix Slaves
Slave 0 Internal SRAM0
Slave 1 Internal SRAM1
Slave 2 Internal ROM
Slave 3 Internal Flash
Slave 4 USB High Speed Dual Port RAM (DPR)
Slave 5 Nand Flash Controller RAM
Slave 6 External Bus Interface
Slave 7 High Speed Peripheral Bridge
Slave 8 Low Speed Peripheral Bridge