Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
296
Commands and read operations can be performed in parallel only on different memory planes. Code can be
fetched from one memory plane while a write or an erase operation is performed on another.
In order to perform one of these commands, the Flash Command Register (EEFC_FCR) has to be written with the
correct command using the FCMD field. As soon as the EEFC_FCR register is written, the FRDY flag and the
FVALUE field in the EEFC_FRR register are automatically cleared. Once the current command is achieved,
then the FRDY flag is automatically set. If an interrupt has been enabled by setting the FRDY bit in EEFC_FMR,
the corresponding interrupt line of the NVIC is activated. (Note that this is true for all commands except for the
STUI Command. The FRDY flag is not set when the STUI command is achieved.)
All the commands are protected by the same keyword, which has to be written in the 8 highest bits of the
EEFC_FCR register.
Writing EEFC_FCR with data that does not contain the correct key and/or with an invalid command has no effect
on the whole memory plane, but the FCMDE flag is set in the EEFC_FSR register. This flag is automatically
cleared by a read access to the EEFC_FSR register.
When the current command writes or erases a page in a locked region, the command has no effect on the whole
memory plane, but the FLOCKE flag is set in the EEFC_FSR register. This flag is automatically cleared by a read
access to the EEFC_FSR register.
Table 18-2. Set of Commands
Command Value Mnemonic
Get Flash Descriptor 0x00 GETD
Write page 0x01 WP
Write page and lock 0x02 WPL
Erase page and write page 0x03 EWP
Erase page and write page then lock 0x04 EWPL
Erase all 0x05 EA
Set Lock Bit 0x08 SLB
Clear Lock Bit 0x09 CLB
Get Lock Bit 0x0A GLB
Set GPNVM Bit 0x0B SGPB
Clear GPNVM Bit 0x0C CGPB
Get GPNVM Bit 0x0D GGPB
Start Read Unique Identifier 0x0E STUI
Stop Read Unique Identifier 0x0F SPUI
Get CALIB Bit 0x10 GCALB