Datasheet

293
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
18.4 Functional Description
18.4.1 Embedded Flash Organization
The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of:
 One memory plane organized in several pages of the same size.
 Two 128-bit or 64-bit read buffers used for code read optimization.
 One 128-bit or 64-bit read buffer used for data read optimization.
 One write buffer that manages page programming. The write buffer size is equal to the page size. This buffer
is write-only and accessible all along the 1 MByte address space, so that each word can be written to its final
address.
 Several lock bits used to protect write/erase operation on several pages (lock region). A lock bit is
associated with a lock region composed of several pages in the memory plane.
 Several bits that may be set and cleared through the Enhanced Embedded Flash Controller (EEFC)
interface, called General Purpose Non Volatile Memory bits (GPNVM bits).
The embedded Flash size, the page size, the lock regions organization and GPNVM bits definition are described in
the product definition section. The Enhanced Embedded Flash Controller (EEFC) returns a descriptor of the Flash
controlled after a get descriptor command issued by the application (see “Getting Embedded Flash Descriptor” on
page 297).
Figure 18-1. Embedded Flash Organization
Start Address
Page 0
Lock Region 0
Lock Region 1
Memory Plane
Page (m-1)
Lock Region (n-1)
Page (n*m-1)
Start Address + Flash size -1
Lock Bit 0
Lock Bit 1
Lock Bit (n-1)