Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
276
The NRSTB pin does not need to be driven during power-up phase to allow a reset of the system, it is done by the
zero-power power-on cell.
Figure 16-6. NRSTB Reset
Note: periph_nreset, ice_reset and proc_nreset are not shown, but are asserted low thanks to the vddcore_nreset signal controlling the
Reset controller.
16.4.6.3 SHDN output pin
As shown in Figure 16-6, the SHDN pin acts like the vr_standby signal making it possible to use the SHDN pin to
control external voltage regulator with shutdown capabilities.
16.4.7 Core Reset
The Supply Controller manages the vddcore_nreset signal to the Reset Controller, as described previously in
Section 16.4.6 ”Backup Power Supply Reset”. The vddcore_nreset signal is normally asserted before shutting
down the core power supply and released as soon as the core power supply is correctly regulated.
There are two additional sources which can be programmed to activate vddcore_nreset:
 a supply monitor detection
 a brownout detection
16.4.7.1 Supply Monitor Reset
The supply monitor is capable of generating a reset of the system. This can be enabled by setting the SMRSTEN
bit in the Supply Controller Supply Monitor Mode Register (SUPC_SMMR).
If SMRSTEN is set and if a supply monitor detection occurs, the vddcore_nreset signal is immediately activated for
a minimum of 1 slow clock cycle.
16.4.7.2 Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the voltage regulation is
operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is
enabled, the Supply Controller can assert vddcore_nreset. This feature is enabled by writing the bit, BODRSTEN
(Brownout Detector Reset Enable) to 1 in the Supply Controller Mode Register (SUPC_MR).
If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset
signal is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. The
BODRSTS bit is set in the Supply Controller Status Register (SUPC_SR) so that the user can know the source of
the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
30 Slow Clock Cycles = about 1ms between 2 and 3 Slow Clock Cycles
32 kHz Low Power Crystal
Oscillator output
NRSTB
SHDN / vr_standby
bodcore_in
vddcore_nreset