Datasheet

271
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
16.4.2 Slow Clock Generator
The Supply Controller embeds a slow clock generator that is supplied with the VDDBU power supply. As soon as
the VDDBU is supplied, both the crystal oscillator and the embedded RC oscillator are powered up, but only the
embedded RC oscillator is enabled. This allows the slow clock to be valid in a short time (about 100 µs).
The user can select the crystal oscillator to be the source of the slow clock, as it provides a more accurate
frequency. The command is made by writing the Supply Controller Control Register (SUPC_CR) with the
XTALSEL bit at 1. This results in a sequence which first enables the crystal oscillator, then waits for 32,768 slow
clock cycles, then switches the slow clock on the output of the crystal oscillator and then disables the RC oscillator
to save power. The switch of the slow clock source is glitch free. The OSCSEL bit of the Supply Controller Status
Register (SUPC_SR) allows knowing when the switch sequence is done.
Coming back on the RC oscillator is only possible by shutting down the VDDBU power supply.
If the user does not need the crystal oscillator, the XIN32 and XOUT32 pins should be left unconnected.
The user can also set the crystal oscillator in bypass mode instead of connecting a crystal. In this case, the user
has to provide the external clock signal on XIN32. The input characteristics of the XIN32 pin are given in the
product electrical characteristics section. In order to set the bypass mode, the OSCBYPASS bit of the Supply
Controller Mode Register (SUPC_MR) needs to be set at 1.
16.4.3 Voltage Regulator Control/Backup Low Power Mode
The Supply Controller can be used to control the embedded 1.8V voltage regulator.
The voltage regulator automatically adapts its quiescent current depending on the required load current. Please
refer to the electrical characteristics section.
The programmer can switch off the voltage regulator, and thus put the device in Backup mode, by writing the
Supply Controller Control Register (SUPC_CR) with the VROFF bit at 1.
This can be done also by using WFE (Wait for Event) Cortex-M3 instruction with the deep mode bit set to 1.
The Backup mode can also be entered by executing the WFI (Wait for Interrupt) or WFE (Wait for Event) Cortex-
M3 instructions. To select the Backup mode entry mechanism, two options are available, depending on the
SLEEPONEXIT bit in the Cortex-M3 System Control register:
 Sleep-now: if the SLEEPONEXIT bit is cleared, the device enters Backup mode as soon as the WFI or WFE
instruction is executed.
 Sleep-on-exit: if the SLEEPONEXIT bit is set when the WFI instruction is executed, the device enters
Backup mode as soon as it exits the lowest priority ISR.
This asserts the vddcore_nreset signal after the write resynchronization time which lasts, in the worse case, two
slow clock cycles. Once the vddcore_nreset signal is asserted, the processor and the peripherals are stopped one
slow clock cycle before the core power supply shuts off.
When the user does not use the internal voltage regulator and wants to supply VDDCORE by an external supply, it
is possible to disable the voltage regulator. Note that it is different from the Backup mode. Depending on the
application, disabling the voltage regulator can reduce power consumption as the voltage regulator input (VDDIN)
is shared with the ADC and DAC. This is done through ONREG bit in SUPC_MR.
16.4.4 Using Backup Batteries/Backup Supply
The product can be used with or without backup batteries, or more generally a backup supply. When a backup
supply is used (See Figure 16-2), only VDDBU voltage is present in Backup mode and no other external supply is
applied on the chip. In this case the user needs to clear VDDIORDY bit in the Supply Controller Mode Register
(SUPC_MR) at least two slow clock periods before VDDIO voltage is removed. When waking up from Backup
mode, the programmer needs to set VDDIORDY.