Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
206
10.23.6 MPU access permission attributes
This section describes the MPU access permission attributes. The access permission bits, TEX, C, B, S, AP, and
XN, of the RASR, control access to the corresponding memory region. If an access is made to an area of memory
without the required permissions, then the MPU generates a permission fault.
Table 10-37 shows the encodings for the TEX, C, B, and S access permission bits.
Table 10-38 shows the cache policy for memory attribute encodings with a TEX value is in the range 4-7.
Table 10-37. TEX, C, B, and S encoding
TEX C B S Memory type Shareability Other attributes
b000
0
0 x
(1)
1. The MPU ignores the value of this bit.
Strongly-ordered Shareable -
1 x
(1)
Device Shareable -
1
0
0
Normal
Not shareable
Outer and inner write-through. No write allocate.
1 Shareable
1
0
Normal
Not shareable
Outer and inner write-back. No write allocate.
1 Shareable
b001
0
0
0
Normal
Not shareable
1 Shareable
1 x
(1)
Reserved encoding -
1
0 x
(1)
Implementation defined attributes. -
1
0
Normal
Not shareable
Outer and inner write-back. Write and read allocate.
1 Shareable
b010
0
0 x
(1)
Device Not shareable Nonshared Device.
1 x
(1)
Reserved encoding -
1x
(1)
x
(1)
Reserved encoding -
b1BB A A
0
Normal
Not shareable
1 Shareable
Table 10-38. Cache policy for memory attribute encoding
Encoding, AA or BB Corresponding cache policy
00 Non-cacheable
01 Write back, write and read allocate
10 Write through, no write allocate
11 Write back, no write allocate