Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
204
10.23.5 MPU Region Attribute and Size Register
The RASR defines the region size and memory attributes of the MPU region specified by the RNR, and enables
that region and any subregions. See the register summary in Table 10-35 on page 198 for its attributes.
RASR is accessible using word or halfword accesses:
 the most significant halfword holds the region attributes
 the least significant halfword holds the region size and the region and subregion enable bits.
The bit assignments are:
•XN
Instruction access disable bit:
0: instruction fetches enabled
1: instruction fetches disabled.
•AP
Access permission field, see Table 10-39 on page 207.
• TEX, C, B
Memory access attributes, see Table 10-37 on page 206.
•S
Shareable bit, see Table 10-36 on page 205.
•SRD
Subregion disable bits. For each bit in this field:
0: corresponding sub-region is enabled
1: corresponding sub-region is disabled
See “Subregions” on page 208 for more information.
Region sizes of 128 bytes and less do not support subregions. When writing the attributes for such a region, write the SRD
field as 0x00.
•SIZE
Specifies the size of the MPU protection region. The minimum permitted value is 3 (b00010), see See “SIZE field values”
on page 205 for more information.
• ENABLE
Region enable bit.
For information about access permission, see “MPU access permission attributes” .
31 302928 27 26 25 24
Reserved XN Reserved AP
23 22 21 20 19 18 17 16
Reserved TEX S CB
15 14 13 12 11 10 9 8
SRD
76543 210
Reserved SIZE ENABLE