Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
200
10.23.2 MPU Control Register
The MPU CTRL register:
 enables the MPU
 enables the default memory map background region
 enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated
handlers.
See the register summary in Table 10-35 on page 198 for the MPU CTRL attributes. The bit assignments are:
• PRIVDEFENA
Enables privileged software access to the default memory map:
0: If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any
enabled region causes a fault.
1: If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.
When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority
over this default map.
If the MPU is disabled, the processor ignores this bit.
•HFNMIENA
Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers.
When the MPU is enabled:
0: MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit
1: the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.
• ENABLE
Enables the MPU:
0: MPU disabled
1: MPU enabled.
When ENABLE and PRIVDEFENA are both set to 1:
For privileged accesses, the default memory map is as described in “Memory model” on page 62. Any access by privileged
software that does not address an enabled memory region behaves as defined by the default memory map.
Any access by unprivileged software that does not address an enabled memory region causes a memory management
fault.
XN and Strongly-ordered rules always apply to the System Control Space regardless of the value of the ENABLE bit.
31 302928 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543 210
Reserved
PRIVDEFENA
HFNMIENA ENABLE