Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
172
10.21.6 Application Interrupt and Reset Control Register
The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset
control of the system. See the register summary in Table 10-30 on page 165 and Table 10-33 on page 192 for its
attributes.
To write to this register, you must write
0x05FA to the VECTKEY field, otherwise the processor ignores the write.
The bit assignments are:
• VECTKEYSTAT
Register Key:
Reads as 0xFA05
• VECTKEY
Register key:
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
• ENDIANESS
RO
Data endianness bit:
0: Little-endian
ENDIANESS is set from the BIGEND configuration signal during reset.
•PRIGROUP
R/W
Interrupt priority grouping field. This field determines the split of group priority from subpriority, see “Binary point” on page
173.
• SYSRESETREQ
WO
System reset request:
0: no effect
1: asserts a proc_reset_signal.
This is intended to force a large system reset of all major components except for debug.
This bit reads as 0.
31 302928 27 26 25 24
On Read: VECTKEYSTAT, On Write: VECTKEY
23 22 21 20 19 18 17 16
On Read: VECTKEYSTAT, On Write: VECTKEY
15 14 13 12 11 10 9 8
ENDIANESS Reserved PRIGROUP
76543 210
Reserved
SYSRESETREQ
VECTCLR-
ACTIVE
VECTRESET