Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
166
10.21.2 Auxiliary Control Register
The ACTLR provides disable bits for the following processor functions:
 IT folding
 write buffer use for accesses to the default memory map
 interruption of multi-cycle instructions.
See the register summary in Table 10-30 on page 165 for the ACTLR attributes. The bit assignments are:
• DISFOLD
When set to 1, disables IT folding. see “About IT folding” on page 166 for more information.
•DISDEFWBUF
When set to 1, disables write buffer use during default memory map accesses. This causes all bus faults to be precise bus
faults but decreases performance because any store to memory must complete before the processor can execute the next
instruction.
This bit only affects write buffers implemented in the Cortex-M3 processor.
• DISMCYCINT
When set to 1, disables interruption of load multiple and store multiple instructions. This increases the interrupt latency of
the processor because any LDM or STM must complete before the processor can stack the current state and enter the
interrupt handler.
10.21.2.1 About IT folding
In some situations, the processor can start executing the first instruction in an IT block while it is still executing the
IT instruction. This behavior is called IT folding, and improves performance, However, IT folding can cause jitter in
looping. If a task must avoid jitter, set the DISFOLD bit to 1 before executing the task, to disable IT folding.
31 302928 27 26 25 24
Reserved
23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8
Reserved
76543 210
Reserved DISFOLD DISDEFWBUF DISMCYCINT