Datasheet

163
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10.20.9 Level-sensitive interrupts
The processor supports level-sensitive interrupts.
A level-sensitive interrupt is held asserted until the peripheral deasserts the interrupt signal. Typically this happens
because the ISR accesses the peripheral, causing it to clear the interrupt request.
When the processor enters the ISR, it automatically removes the pending state from the interrupt, see “Hardware
and software control of interrupts” . For a level-sensitive interrupt, if the signal is not deasserted before the
processor returns from the ISR, the interrupt becomes pending again, and the processor must execute its ISR
again. This means that the peripheral can hold the interrupt signal asserted until it no longer needs servicing.
10.20.9.1 Hardware and software control of interrupts
The Cortex-M3 latches all interrupts. A peripheral interrupt becomes pending for one of the following reasons:
 the NVIC detects that the interrupt signal is HIGH and the interrupt is not active
 the NVIC detects a rising edge on the interrupt signal
 software writes to the corresponding interrupt set-pending register bit, see “Interrupt Set-pending Registers”
on page 157, or to the STIR to make an SGI pending, see “Software Trigger Interrupt Register” on page 162.
A pending interrupt remains pending until one of the following:
The processor enters the ISR for the interrupt. This changes the state of the interrupt from pending to active. Then:
 For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC samples the
interrupt signal. If the signal is asserted, the state of the interrupt changes to pending, which might
cause the processor to immediately re-enter the ISR. Otherwise, the state of the interrupt changes to
inactive.
 If the interrupt signal is not pulsed while the processor is in the ISR, when the processor returns from
the ISR the state of the interrupt changes to inactive.
 Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the interrupt does not change.
Otherwise, the state of the interrupt changes to inactive.