Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
156
10.20.3 Interrupt Clear-enable Registers
The ICER0-ICER1 register disables interrupts, and shows which interrupts are enabled. See:
 the register summary in Table 10-27 on page 153 for the register attributes
 Table 10-28 on page 154 for which interrupts are controlled by each register
The bit assignments are:
•CLRENA
Interrupt clear-enable bits.
Write:
0: no effect
1: disable interrupt.
Read:
0: interrupt disabled
1: interrupt enabled.
31 302928 27 26 25 24
CLRENA
23 22 21 20 19 18 17 16
CLRENA
15 14 13 12 11 10 9 8
CLRENA
76543 210
CLRENA