Datasheet

155
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10.20.2 Interrupt Set-enable Registers
The ISER0-ISER1 register enables interrupts, and show which interrupts are enabled. See:
 the register summary in Table 10-27 on page 153 for the register attributes
 Table 10-28 on page 154 for which interrupts are controlled by each register.
The bit assignments are:
• SETENA
Interrupt set-enable bits.
Write:
0: no effect
1: enable interrupt.
Read:
0: interrupt disabled
1: interrupt enabled.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, assert-
ing its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its
priority.
31 302928 27 26 25 24
SETENA bits
23 22 21 20 19 18 17 16
SETENA bits
15 14 13 12 11 10 9 8
SETENA bits
76543 210
SETENA bits