Datasheet

153
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no
instruction overhead. This provides low latency exception handling. The hardware implementation of the NVIC
registers is:
10.20.1 The CMSIS mapping of the Cortex-M3 NVIC registers
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
 the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of 32-bit
integers, so that:
 the array
ISER[0] to ISER[1] corresponds to the registers ISER0-ISER1
 the array
ICER[0] to ICER[1] corresponds to the registers ICER0-ICER1
 the array
ISPR[0] to ISPR[1] corresponds to the registers ISPR0- ISPR1
 the array ICPR[0] to ICPR[1] corresponds to the registers ICPR0- ICPR1
 the array IABR[0] to IABR[1] corresponds to the registers IABR0- IABR1
 the 4-bit fields of the Interrupt Priority Registers map to an array of 4-bit integers, so that the array IP[0] to
IP[29] corresponds to the registers IPR0-IPR7, and the array entry IP[n] holds the interrupt priority for
interrupt n.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For more
information see the description of the NVIC_SetPriority function in “NVIC programming hints” on page 164. Table
10-28 shows how the interrupts, or IRQ numbers, map onto the interrupt registers and corresponding CMSIS
variables that have one bit per interrupt.
Table 10-27. NVIC register summary
Address Name Type Required privilege Reset value Description
0xE000E100 -
0xE000E104
ISER0-
ISER1
RW Privileged 0x00000000 “Interrupt Set-enable Registers” on page 155
0xE000E180-
0xE000E184
ICER0-
ICER1
RW Privileged 0x00000000 “Interrupt Clear-enable Registers” on page 156
0xE000E200-
0xE000E204
ISPR0-
ISPR1
RW Privileged 0x00000000 “Interrupt Set-pending Registers” on page 157
0xE000E280-
0xE000E284
ICPR0-
ICPR1
RW Privileged 0x00000000 “Interrupt Clear-pending Registers” on page 158
0xE000E300-
0xE000E304
IABR0-
IABR1
RO Privileged 0x00000000 “Interrupt Active Bit Registers” on page 159
0xE000E400-
0xE000E41C
IPR0-
IPR7
RW Privileged 0x00000000 “Interrupt Priority Registers” on page 160
0xE000EF00 STIR WO Configurable
(1)
0x00000000 “Software Trigger Interrupt Register” on page 162
1. See the register description for more information.