Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
152
10.19 About the Cortex-M3 peripherals
The address map of the Private peripheral bus (PPB) is:
In register descriptions:
 the register type is described as follows:
RW Read and write.
RO Read-only.
WO Write-only.
 the required privilege gives the privilege level required to access the register, as follows:
Privileged Only privileged software can access the register.
Unprivileged Both unprivileged and privileged software can access the register.
10.20 Nested Vectored Interrupt Controller
This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it uses. The NVIC
supports:
 1 to 30 interrupts.
 A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a lower priority, so
level 0 is the highest interrupt priority.
 Level detection of interrupt signals.
 Dynamic reprioritization of interrupts.
 Grouping of priority values into group priority and subpriority fields.
 Interrupt tail-chaining.
Table 10-26. Core peripheral register regions
Address Core peripheral Description
0xE000E008 -
0xE000E00F
System control block Table 10-30 on page 165
0xE000E010 -
0xE000E01F
System timer Table 10-33 on page 192
0xE000E100 -
0xE000E4EF
Nested Vectored Interrupt
Controller
Table 10-27 on page 153
0xE000ED00 -
0xE000ED3F
System control block Table 10-30 on page 165
0xE000ED90 -
0xE000EDB8
Memory protection unit Table 10-35 on page 198
0xE000EF00 -
0xE000EF03
Nested Vectored Interrupt
Controller
Table 10-27 on page 153