Datasheet

DRAFT
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1428
Table 45-57. USART SPI Timings
Symbol Parameter Conditions Min Max Unit
Master Mode
SPI
0
t
CPSCK
Period
1.8V domain
3.3V domain
t
CPMCK
/ 6 ns
SPI
1
Input Data Setup Time
1.8V domain
3.3V domain
0.5 × t
CPMCK
+ 7.7 ns
SPI
2
Input Data Hold Time
1.8V domain
3.3V domain
1.5 × t
CPMCK
+ 1.8
1.5 × t
CPMCK
+ 0.7
ns
SPI
3
Chip Select Active to Serial Clock
1.8V domain
3.3V domain
1.5 × t
CPSCK
-1 ns
SPI
4
Output Data Setup Time
1.8V domain
3.3V domain
07.4ns
SPI
5
Serial Clock to Chip Select Inactive
1.8V domain
3.3V domain
1 × t
CPSCK
- 1 ns
Slave Mode
SPI
6
t
CPSCK
falling to MISO
1.8V domain
3.3V domain
730ns
SPI
7
MOSI Setup time before t
CPSCK
rises
1.8V domain
3.3V domain
2 × t
CPMCK
+ 6.8 ns
SPI
8
MOSI Hold time after t
CPSCK
rises
1.8V domain
3.3V domain
1ns
SPI
9
t
CPSCK
rising to MISO
1.8V domain
3.3V domain
7ns
SPI
10
MOSI Setup time before t
CPSCK
falls
1.8V domain
3.3V domain
2 × t
CPMCK
+ 6 ns
SPI
11
MOSI Hold time after t
CPSCK
falls
1.8V domain
3.3V domain
2.7
1
ns
SPI
12
NPCS0 setup to t
CPSCK
rising
1.8V domain
3.3V domain
2.5 × t
CPMCK
+1 ns
SPI
13
NPCS0 hold after t
CPSCK
falling
1.8V domain
3.3V domain
1.5 × t
CPMCK
+ 4 ns
SPI
14
NPCS0 setup to t
CPSCK
falling
1.8V domain
3.3V domain
2.5 × t
CPMCK
+ 0.4 ns
SPI
15
NPCS0 hold after t
CPSCK
rising
1.8V domain
3.3V domain
1.5 × t
CPMCK
+ 2.7 ns