Datasheet
DRAFT
1425
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
Notes: 1. 3V domain: V
DDIO
from 3.0V to 3.6V, maximum external capacitor on data, control and address = 50 pF, maximum
external capacitor on clock = 10 pF
2. 3.3V domain: V
DDIO
from 3.3V to 3.6V, maximum external capacitor on data, control and address = 50 pF,
maximum external capacitor on clock = 10 pF
3. Control is the tNSSet of following signals : SDCKE, SDCS, RAS, CAS, SDA10, BAx, DQMx, and SDWE
4. Address is the set of A0–A9, A11–A13
Notes: 1. 3V domain: V
DDIO
from 3.0V to 3.6V, maximum external capacitor on data, control and address = 50 pF, maximum
external capacitor on clock = 10 pF
2. 3.3V domain: V
DDIO
from 3.3V to 3.6V, maximum external capacitor on data, control and address = 50 pF,
maximum external capacitor on clock = 10 pF
3. Control is the tNSSet of following signals: SDCKE, SDCS, RAS, CAS, SDA10, BAx, DQMx, and SDWE
4. Address is the set of A0–A9, A11–A13
Notes: 1. 1.8V domain: V
DDIO
from 1.62V to 1.95V, maximum external capacitor on data, control and address = 30 pF,
maximum external capacitor on clock = 10 pF
2. Control is the tNSSet of following signals : SDCKE, SDCS, RAS, CAS, SDA10, BAx, DQMx, and SDWE
3. Address is the set of A0–A9, A11–A13
Table 45-54. SDRAM PC100 Characteristics
Parameter
Min Max
Unit3V Supply
(1)
3V Supply
(1)
3.3V Supply
(2)
SDRAM Controller Clock Frequency 76.9 92 MHz
Control/Address/Data In Setup
(3)(4)
2ns
Control/Address/Data In Hold
(3)(4)
1ns
Data Out Access time after SDCK rising 6 6 ns
Data Out change time after SDCK rising 3 ns
Table 45-55. SDRAM PC133 Characteristics
Parameter
Min Max
Unit3V Supply
(1)
3V Supply
(1)
3.3V Supply
(2)
SDRAM Controller Clock Frequency 80.6 100 MHz
Control/Address/Data In Setup
(3)(4)
1.5 ns
Control/Address/Data In Hold
(3)(4)
0.8 ns
Data Out Access time after SDCK rising 5.4 5.4 ns
Data Out change time after SDCK rising 3.0 ns
Table 45-56. Mobile Characteristics
Parameter
Min Max
Unit1.62V Supply
(1)
1.62V Supply
(1)
1.8V Supply
(1)
SDRAM Controller Clock Frequency 71.9 84 MHz
Control/Address/Data In Setup
(2)(3)
1.5 ns
Control/Address/Data In Hold
(2)(3)
1ns
Data Out Access time after SDCK rising 6 6 ns
Data Out change time after SDCK rising 2.5 ns