Datasheet

DRAFT
1423
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
45.10.6.2 Write Timings
Notes: 1. Hold length = total cycle duration - setup duration - pulse duration. “Hold length” is for “NCS_WR_HOLD length” or
“NWE_HOLD length”.
Table 45-52. SMC Write Signals - NWE Controlled (WRITE_MODE = 1)
Symbol
Parameter Min Max
UnitVDDIO supply 1.8V Domain 3.3V Domain 1.8V Domain 3.3V Domain
HOLD or NO HOLD SETTINGS (NWE_HOLD ≠ 0, NWE_HOLD = 0)
SMC
15
Data Out Valid before NWE High NWE_PULSE × t
CPMCK
- 7.5 NWE_PULSE × t
CPMCK
- 7 ns
SMC
16
NWE Pulse Width NWE_PULSE × t
CPMCK
- 3 NWE_PULSE × t
CPMCK
- 3 ns
SMC
17
NBS0/A0 NBS1, NBS2/A1, NBS3,
A2–A25 valid before NWE low
NWE_SETUP × t
CPMCK
+ 6 NWE_SETUP × t
CPMCK
+ 6 ns
SMC
18
NCS low before NWE high
(NWE_SETUP -
NCS_RD_SETUP +
NWE_PULSE) × t
CPMCK
+ 10
(NWE_SETUP -
NCS_RD_SETUP +
NWE_PULSE) × t
CPMCK
+ 12
ns
HOLD SETTINGS (NWE_HOLD ≠ 0)
SMC
19
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2–A25
change
NWE_HOLD × t
CPMCK
- 2.4 NWE_HOLD × t
CPMCK
- 1.8 ns
SMC
20
NWE High to NCS Inactive
(1)
(NWE_HOLD - NCS_WR_HOLD)
× t
CPMCK
- 0.3
(NWE_HOLD - NCS_WR_HOLD)
× t
CPMCK
- 0.3
ns
NO HOLD SETTINGS (NWE_HOLD = 0)
SMC
21
NWE High to Data OUT, NBS0/A0
NBS1, NBS2/A1, NBS3, A2–A25,
NCS change
(1)
44 ns
Table 45-53. SMC Write NCS Controlled (WRITE_MODE = 0)
Symbol
Parameter Min Max
UnitVDDIO supply 1.8V Domain 3.3V Domain 1.8V Domain 3.3V Domain
SMC
22
Data Out Valid before NCS High NCS_WR_PULSE × t
CPMCK
- 1 NCS_WR_PULSE × t
CPMCK
- 1 ns
SMC
23
NCS Pulse Width NCS_WR_PULSE × t
CPMCK
- 6 NCS_WR_PULSE × t
CPMCK
- 6 ns
SMC
24
NBS0/A0 NBS1, NBS2/A1, NBS3,
A2–A25 valid before NCS low
NCS_WR_SETUP × t
CPMCK
- 5 NCS_WR_SETUP × t
CPMCK
- 5 ns
SMC
25
NWE low before NCS high
(NCS_WR_SETUP -
NWE_SETUP + NCS pulse) ×
t
CPMCK
+ 1.3
(NCS_WR_SETUP -
NWE_SETUP + NCS pulse) ×
t
CPMCK
+ 1.3
ns
SMC
26
NCS High to Data Out, NBS0/A0,
NBS1, NBS2/A1, NBS3, A2–A25,
change
NCS_WR_HOLD × t
CPMCK
- 8.2 NCS_WR_HOLD × t
CPMCK
- 9.6 ns
SMC
27
NCS High to NWE Inactive
(NCS_WR_HOLD - NWE_HOLD)
× t
CPMCK
- 6.2
(NCS_WR_HOLD - NWE_HOLD)
× t
CPMCK
- 9
ns