Datasheet

139
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
10.17.4 TBB and TBH
Table Branch Byte and Table Branch Halfword.
10.17.4.1 Syntax
TBB [Rn, Rm]
TBH [Rn, Rm, LSL #1]
where:
Rn is the register containing the address of the table of branch lengths. If Rn is PC, then the address of
the table is the address of the byte immediately following the TBB or TBH instruction.
Rm is the index register. This contains an index into the table. For halfword tables, LSL #1 doubles the
value in Rm to form the right offset into the table.
10.17.4.2 Operation
These instructions cause a PC-relative forward branch using a table of single byte offsets for TBB, or halfword
offsets for TBH. Rn provides a pointer to the table, and Rm supplies an index into the table. For TBB the branch
offset is twice the unsigned value of the byte returned from the table. and for TBH the branch offset is twice the
unsigned value of the halfword returned from the table. The branch occurs to the address at that offset from the
address of the byte immediately after the TBB or TBH instruction.
10.17.4.3 Restrictions
The restrictions are:
 Rn must not be SP
 Rm must not be SP and must not be PC
 when any of these instructions is used inside an IT block, it must be the last instruction of the IT block.
10.17.4.4 Condition flags
These instructions do not change the flags.