Datasheet

1201
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
 Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over.
 Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of
frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register.
All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and
the timestamp interrupt. These interrupts are cleared by reading the CAN_SR register.
40.8.3 CAN Controller Message Handling
40.8.3.1 Receive Handling
Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message
received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is
stored in the mailbox.
Simple Receive Mailbox
A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID
and Message Acceptance Mask must be set before the Receive Mode is enabled.
After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first
message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An
interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the
mailbox flag in the CAN_IMR global register.
Message data are stored in the mailbox data register until the software application notifies that data processing
has ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx register.
This automatically clears the MRDY signal.
The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This
flag is set when messages are received while MRDY is set in the CAN_MSRx register. This flag is cleared by
reading the CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while
MRDY flag is set in the CAN_MSRx register. See Figure 40-11.
Figure 40-11. Receive Mailbox
Note: In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler
instruction.
Message 1 Message 2 lostMessage 3
Message 3
Message 1
Reading CAN_MSRx
Reading CAN_MDHx & CAN_MDLx
Writing CAN_MCRx
MMI
(CAN_MSRx)
MRDY
(CAN_MSRx)
CAN BUS
(CAN_MDLx
CAN_MDHx)
MTCR
(CAN_MCRx)
Message ID = CAN_MIDx