Datasheet
1181
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
39.6.3.24 Host DMA Channel x Control Register
Name: UOTGHS_HSTDMACONTROLx [x=1..6]
Address: 0x400AC718 [1], 0x400AC728 [2], 0x400AC738 [3], 0x400AC748 [4], 0x400AC758 [5], 0x400AC768 [6],
0x400AC778 [7]
Access: Read-write
• CHANN_ENB: Channel Enable Command
0: DMA channel is disabled and no transfer will occur upon request. This bit is also cleared by hardware when the channel
source bus is disabled at the end of buffer.
If LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to set the corresponding CHANN_ENB
bit to start the described transfer, if needed.
If LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as
soon as both UOTGHS_HSTDMASTATUS.CHANN_ENB and CHANN_ACT flags read as 0.
If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then
UOTGHS_HSTDMASTATUS.CHANN_ENB bit is cleared.
If LDNXT_DSC bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs)
and the next descriptor is immediately loaded.
1: UOTGHS_HSTDMASTATUS.CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pending
request will start the transfer. This may be used to start or resume any requested transfer.
• LDNXT_DSC: Load Next Channel Transfer Descriptor Enable Command
0: no channel register is loaded after the end of the channel transfer.
1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the
UOTGHS_HSTDMASTATUS.CHANN_ENB bit is reset.
If CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request.
DMA Channel Control Command Summary
31 30 29 28 27 26 25 24
BUFF_LENGTH
23 22 21 20 19 18 17 16
BUFF_LENGTH
15 14 13 12 11 10 9 8
––––––––
76543210
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB
Value Name Description
0STOP_NOW Stop now
1 RUN_AND_STOP Run and stop at end of buffer
2 LOAD_NEXT_DESC Load next descriptor now
3 RUN_AND_LINK Run and link at end of buffer