Datasheet

1163
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
39.6.3.14 Host Pipe x Status Register
Name: UOTGHS_HSTPIPISRx [x=0..9]
Address: 0x400AC530
Access: Read-only
• PBYCT: Pipe Byte Count
This field contains the byte count of the FIFO.
For OUT pipe, incremented after each byte written by the user into the pipe and decremented after each byte sent to the
peripheral.
For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user
from the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt
bit.
• CFGOK: Configuration OK Status
This bit is set/cleared when the UOTGHS_HSTPIPCFGx.ALLOC bit is set.
This bit is set if the pipe x number of banks (UOTGHS_HSTPIPCFGx.PBK) and size (UOTGHS_HSTPIPCFGx.PSIZE) are
correct compared to the maximal allowed number of banks and size for this pipe and to the maximal FIFO size (i.e., the
DPRAM size).
If this bit is cleared, the user should rewrite correct values of the PBK and PSIZE field in the UOTGHS_HSTPIPCFGx
register.
• RWALL: Read-write Allowed
For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALLDI or the PERRI bit is one.
31 30 29 28 27 26 25 24
– PBYCT
23 22 21 20 19 18 17 16
PBYCT – CFGOK – RWALL
15 14 13 12 11 10 9 8
CURRBK NBUSYBK – – DTSEQ
76543210
SHORTPACKET
I
RXSTALLDI/
CRCERRI
OVERFI NAKEDI PERRI
TXSTPI/
UNDERFI
TXOUTI RXINI