Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1142
39.6.3 USB Host Registers
39.6.3.1 Host General Control Register
Name: UOTGHS_HSTCTRL
Address: 0x400AC400
Access: Read-write
• SPDCONF: Mode Configuration
This field contains the host speed capability:.
• RESUME: Send USB Resume
Writing a one to this bit will generate a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit has no effect.
This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).
• RESET: Send USB Reset
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (UOTGHS_HSTISR.DDISCI is one)
whereas a USB Reset is being sent.
• SOFE: Start of Frame Generation Enable
Writing a one to this bit will generate SOF on the USB bus in full or high speed mode and keep alive in low speed mode.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UOTGHS_HSTISR.TXRSMI).
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– – SPDCONF – RESUME RESET SOFE
76543210
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Value Name Description
0NORMAL
The host starts in full-speed mode and performs a high-speed reset to switch to the high-
speed mode if the downstream peripheral is high-speed capable.
1 LOW_POWER For a better consumption, if high-speed is not needed.
2 HIGH_SPEED Forced high speed.
3 FORCED_FS The host remains to full-speed mode whatever the peripheral speed capability.