Datasheet

1107
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
39.6.2.5 Device Global Interrupt Mask Register
Name: UOTGHS_DEVIMR
Address: 0x400AC010
Access: Read-only
• DMA_x: DMA Channel x Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when DMA_x bit in UOTGHS_DEVIER is written to one.
This bit is cleared when DMA_x bit in UOTGHS_DEVIDR is written to one.
• PEP_x: Endpoint x Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when PEP_x bit in UOTGHS_DEVIER is written to one.
This bit is cleared when PEP_x bit in UOTGHS_DEVIDR is written to one.
• UPRSME: Upstream Resume Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when UPRSMES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when UPRSMEC bit in UOTGHS_DEVIDR is written to one.
• EORSME: End of Resume Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when EORSMES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when EORSMEC bit in UOTGHS_DEVIDR is written to one.
• WAKEUPE: Wake-Up Interrupt Mask
0: The interrupt is disabled.
1: The interrupt is enabled.
This bit is set when WAKEUPES bit in UOTGHS_DEVIER is written to one.
This bit is cleared when WAKEUPEC bit in UOTGHS_DEVIDR is written to one.
31 30 29 28 27 26 25 24
– DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 –
23 22 21 20 19 18 17 16
– – PEP_9 PEP_8 PEP_7 PEP_6 PEP_5 PEP_4
15 14 13 12 11 10 9 8
PEP_3PEP_2PEP_1PEP_0––––
76543210
– UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE