Datasheet

1085
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
Figure 39-29. Example of DMA Chained List
39.5.5 USB DMA Channel Transfer Descriptor
The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer. The
structure of the DMA channel transfer descriptor is defined by three parameters as described below:
Offset 0:
 The address must be aligned: 0xXXXX0
 Next Descriptor Address Register: UOTGHS_xxxDMANXTDSCx
Offset 4:
 The address must be aligned: 0xXXXX4
 DMA Channelx Address Register: UOTGHS_xxxDMAADDRESSx
Offset 8:
 The address must be aligned: 0xXXXX8
 DMA Channelx Control Register: UOTGHS_xxxDMACONTROLx
To use the DMA channel transfer descriptor, fill the structures with the correct value (as described in the following
pages). Then write directly in UOTGHS_xxxDMANXTDSCx the address of the descriptor to be used first.
Then write 1 in UOTGHS_xxxDMACONTROLx.LDNXT_DSC bit (load next channel transfer descriptor). The
descriptor is automatically loaded upon pipe x / endpoint x request for packet transfer.
Data Buffer 1
Data Buffer 2
Data Buffer 3
Memory Area
Transfer Descriptor
Next Descriptor Address
AHB Address
Control
Transfer Descriptor
Transfer Descriptor
USB DMA Channel X Registers
(Current Transfer Descriptor)
Next Descriptor Address
AHB Address
Control
NULL
Status
Next Descriptor Address
AHB Address
Control
Next Descriptor Address
AHB Address
Control