Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1084
The exception host pipe interrupts are:
 The Underflow Interrupt (UOTGHS_HSTPIPISRx.UNDERFI)
 The Pipe Error Interrupt (UOTGHS_HSTPIPISRx.PERRI)
 The NAKed Interrupt (UOTGHS_HSTPIPISRx.NAKEDI)
 The Overflow Interrupt (UOTGHS_HSTPIPISRx.OVERFI)
 The Received STALLed Interrupt (UOTGHS_HSTPIPISRx.RXSTALLDI)
 The CRC Error Interrupt (UOTGHS_HSTPIPISRx.CRCERRI)
DMA interrupts
The processing host DMA interrupts are:
 The End of USB Transfer Status (UOTGHS_HSTDMASTATUSx.END_TR_ST) interrupt
 The End of Channel Buffer Status (UOTGHS_HSTDMASTATUSx.END_BF_ST) interrupt
 The Descriptor Loaded Status (UOTGHS_HSTDMASTATUSx.DESC_LDST) interrupt
There is no exception host DMA interrupt.
39.5.4 USB DMA Operation
USB packets of any length may be transferred when required by the UOTGHS. These transfers always feature
sequential addressing. These two characteristics mean that in case of high UOTGHS throughput, both AHB ports
will benefit from “incrementing burst of unspecified length” since the average access latency of AHB slaves can
then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data transfers and
channel descriptor loading. A burst may last on the AHB busses for the duration of a whole USB packet transfer,
unless otherwise broken by the AHB arbitration or the AHB 1 kbyte boundary crossing.
Packet data AHB bursts may be locked on a DMA buffer basis for drastic overall AHB bus bandwidth performance
boost with paged memories. This is because these memory row (or bank) changes, which are very clock-cycle
consuming, will then likely not occur or occur once instead of dozens of times during a single big USB packet DMA
transfer in case other AHB masters address the memory. This means up to 128 words single cycle unbroken AHB
bursts for bulk pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints. This
maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
(UOTGHS_HSTPIPCFGx.PSIZE / UOTGHS_DEVEPTCFGx.EPSIZE) and the Buffer Byte Length
(UOTGHS_HSTDMACONTROLx.BUFF_LENGTH / UOTGHS_DEVDMACONTROLx.BUFF_LENGTH) field.
The UOTGHS average throughput may be up to nearly 480 Mbps. Its average access latency decreases as burst
length increases due to the zero wait-state side effect of unchanged pipe/endpoint. Word access allows reducing
the AHB bandwidth required for the USB by four, as compared to native byte access. If at least 0 wait-state word
burst capability is also provided by the other DMA AHB bus slaves, each of both DMA AHB busses need less than
60% bandwidth allocation for full USB bandwidth usage at 33 MHz, and less than 30% at 66 MHz.