Datasheet

1083
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
Figure 39-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
39.5.3.12 CRC Error
This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt (UOTGHS_HSTPIPISRx.CRCERRI)
bit, which triggers a PEP_x interrupt if then the CRC Error Interrupt Enable (UOTGHS_HSTPIPIMRx.CRCERRE)
bit is one.
A CRC error can occur during IN stage if the UOTGHS detects a corrupted received packet. The IN packet is
stored in the bank as if no CRC error had occurred (UOTGHS_HSTPIPISRx.RXINI is set).
39.5.3.13 Interrupts
See the structure of the USB host interrupt system on Figure 39-6 on page 1059.
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal processing, and
exception, i.e. errors (not related to CPU exceptions).
Global interrupts
The processing host global interrupts are:
 The Device Connection Interrupt (UOTGHS_HSTISR.DCONNI)
 The Device Disconnection Interrupt (UOTGHS_HSTISR.DDISCI)
 The USB Reset Sent Interrupt (UOTGHS_HSTISR.RSTI)
 The Downstream Resume Sent Interrupt (UOTGHS_HSTISR.RSMEDI)
 The Upstream Resume Received Interrupt (UOTGHS_HSTISR.RXRSMI)
 The Host Start of Frame Interrupt (UOTGHS_HSTISR.HSOFI)
 The Host Wake-Up Interrupt (UOTGHS_HSTISR.HWUPI)
 The Pipe x Interrupt (UOTGHS_HSTISR.PEP_x)
 The DMA Channel x Interrupt (UOTGHS_HSTISR.DMAxINT)
There is no exception host global interrupt.
Pipe interrupts
The processing host pipe interrupts are:
 The Received IN Data Interrupt (UOTGHS_HSTPIPISRx.RXINI)
 The Transmitted OUT Data Interrupt (UOTGHS_HSTPIPISRx.TXOUTI)
 The Transmitted SETUP Interrupt (UOTGHS_HSTPIPISRx.TXSTPI)
 The Short Packet Interrupt (UOTGHS_HSTPIPISRx.SHORTPACKETI)
 The Number of Busy Banks (UOTGHS_HSTPIPISRx.NBUSYBK) interrupt
OUT
DATA
(bank 0)
ACK
write data to CPU
BANK 0
SW
SW SW
SW
OUT
DATA
(bank 1)
ACK
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
UOTGHS_HSTPIPISRx.TXOUTI
UOTGHS_HSTPIPIMRx.FIFOCON