Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1082
39.5.3.11 Management of OUT Pipes
OUT packets are sent by the host. All data which acknowledges or not the bank can be written when it is full.
The pipe must be configured and unfrozen first.
The Transmitted OUT Data Interrupt (UOTGHS_HSTPIPISRx.TXOUTI) bit is set at the same time as
UOTGHS_HSTPIPIMRx.FIFOCON when the current bank is free. This triggers a PEP_x interrupt if the
Transmitted OUT Data Interrupt Enable (UOTGHS_HSTPIPIMRx.TXOUTE) bit is one.
UOTGHS_HSTPIPISRx.TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data
Interrupt Clear (UOTGHS_HSTPIPIDRx.TXOUTIC) bit) to acknowledge the interrupt, which has no effect on the
pipe FIFO.
The user then writes into the FIFO and clears the UOTGHS_HSTPIPIDRx.FIFOCON bit to allow the UOTGHS to
send the data. If the OUT pipe is composed of multiple banks, this also switches to the next bank. The
UOTGHS_HSTPIPISRx.TXOUTI and UOTGHS_HSTPIPIMRx.FIFOCON bits are updated in accordance with the
status of the next bank.
UOTGHS_HSTPIPISRx.TXOUTI shall always be cleared before clearing UOTGHS_HSTPIPIMRx.FIFOCON.
The UOTGHS_HSTPIPISRx.RWALL bit is set when the current bank is not full, i.e., the software can write further
data into the FIFO.
Notes: 1. If the user decides to switch to the Suspend state (by writing a zero to the UOTGHS_HSTCTRL.SOFE bit) while a
bank is ready to be sent, the UOTGHS automatically exits this state and the bank is sent.
2. In High-Speed operating mode, the host controller automatically manages the PING protocol to maximize the
USB bandwidth. The user can tune the PING protocol by handling the Ping Enable (PINGEN) bit and the bInterval
Parameter for the Bulk-Out/Ping Transaction (BINTERVALL) field in UOTGHS_HSTPIPCFGx. See the Section
39.6.3.13 for more details.
Figure 39-26. Example of an OUT Pipe with one Data Bank
Figure 39-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
OUT
DATA
(bank 0)
ACK
HW
write data to CPU
BANK 0
SW
SW SW
SW
OUT
write data to CPU
BANK 0
UOTGHS_HSTPIPISRx.TXOUTI
UOTGHS_HSTPIPIMRx.FIFOCON
OUT
DATA
(bank 0)
ACK
write data to CPU
BANK 0
SW
SW SW
SW
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
OUT
DATA
(bank 1)
ACK
UOTGHS_HSTPIPISRx.TXOUTI
UOTGHS_HSTPIPIMRx.FIFOCON