Datasheet

1081
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
When the host requires data from the device, the user has to select beforehand the IN request mode with the IN
Request Mode bit in the Pipe x IN Request register (UOTGHS_HSTPIPINRQx.INMODE):
 When UOTGHS_HSTPIPINRQx.INMODE is written to zero, the UOTGHS will perform (INRQ + 1) IN
requests before freezing the pipe.
 When UOTGHS_HSTPIPINRQx.INMODE is written to one, the UOTGHS will perform IN requests endlessly
when the pipe is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze
(UOTGHS_HSTPIPIMRx.PFREEZE) field in UOTGHS_HSTPIPIMRx is zero).
The Received IN Data Interrupt (UOTGHS_HSTPIPISRx.RXINI) bit is set at the same time as the FIFO Control
(UOTGHS_HSTPIPIMRx.FIFOCON) bit when the current bank is full. This triggers a PEP_x interrupt if the
Received IN Data Interrupt Enable (UOTGHS_HSTPIPIMRx.RXINE) bit is one.
UOTGHS_HSTPIPISRx.RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt
Clear bit in the Host Pipe x Clear register (UOTGHS_HSTPIPIDRx.RXINIC)) to acknowledge the interrupt, which
has no effect on the pipe FIFO.
The user then reads from the FIFO and clears the UOTGHS_HSTPIPIMRx.FIFOCON bit (by writing a one to the
FIFO Control Clear (UOTGHS_HSTPIPIDRx.FIFOCONC) bit) to free the bank. If the IN pipe is composed of
multiple banks, this also switches to the next bank. The UOTGHS_HSTPIPISRx.RXINI and
UOTGHS_HSTPIPIMRx.FIFOCON bits are updated in accordance with the status of the next bank.
UOTGHS_HSTPIPISRx.RXINI shall always be cleared before clearing UOTGHS_HSTPIPIMRx.FIFOCON.
The Read-write Allowed (UOTGHS_HSTPIPISRx.RWALL) bit is set when the current bank is not empty, i.e., the
software can read further data from the FIFO.
Figure 39-24. Example of an IN Pipe with 1 Data Bank
Figure 39-25. Example of an IN Pipe with 2 Data Banks
IN
DATA
(bank 0)
ACK
UOTGHS_HSTPIPISRx.RXINI
UOTGHS_HSTPIPIMRx.FIFOCON
HW
IN
DATA
(bank 0)
ACK
HW
SW
SW
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
IN
DATA
(bank 0)
ACK
HW
IN
DATA
(bank 1)
ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1
UOTGHS_HSTPIPISRx.RXINI
UOTGHS_HSTPIPIMRx.FIFOCON