Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1080
See Section 39.5.1.6 for more details about DPRAM management.
Once the pipe is correctly configured (UOTGHS_HSTPIPISRx.CFGOK is one), only the
UOTGHS_HSTPIPCFGx.PTOKEN and UOTGHS_HSTPIPCFGx.INTFRQ fields can be written by software.
UOTGHS_HSTPIPCFGx.INTFRQ is meaningless for non-interrupt pipes.
When starting an enumeration, the user gets the device descriptor by sending a GET_DESCRIPTOR USB
request. This descriptor contains the maximal packet size of the device default control endpoint
(bMaxPacketSize0) and the user re-configures the size of the default control pipe with this size parameter.
39.5.3.7 Address Setup
Once the device has answered the first host requests with default device address 0, the host assigns a new
address to the device. The host controller has to send a USB reset to the device and to send a SET_ADDRESS
(addr) SETUP request with the new address to be used by the device. Once this SETUP transaction is over, the
user writes the new address into the USB Host Address for Pipe x field in the USB Host Device Address register
(HSTADDR.HSTADDRPx). All following requests, on all pipes, will be performed using this new address.
When the host controller sends a USB reset, the HSTADDRPx field is reset by hardware and the following host
requests will be performed using default device address 0.
39.5.3.8 Remote Wake-up
The controller host mode enters the Suspend state when the UOTGHS_HSTCTRL.SOFE bit is written to zero. No
more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend state 3 ms later.
The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature). When the host
controller detects a non-idle state on the USB bus, it sets the Host Wake-Up interrupt (UOTGHS_HSTISR.HWUPI)
bit. If the non-idle bus state corresponds to an Upstream Resume (K state), the Upstream Resume Received
Interrupt (UOTGHS_HSTISR.RXRSMI) bit is set. The user has to generate a Downstream Resume within 1 ms
and for at least 20 ms by writing a one to the Send USB Resume (UOTGHS_HSTCTRL.RESUME) bit. It is
mandatory to write a one to UOTGHS_HSTCTRL.SOFE before writing a one to UOTGHS_HSTCTRL.RESUME to
enter the Ready state, else UOTGHS_HSTCTRL.RESUME will have no effect.
39.5.3.9 Management of Control Pipes
A control transaction is composed of three stages:
 SETUP
 Data (IN or OUT)
 Status (OUT or IN)
The user has to change the pipe token according to each stage.
For the control pipe, and only for it, each token is assigned a specific initial data toggle sequence:
 SETUP: Data0
 IN: Data1
 OUT: Data1
39.5.3.10 Management of IN Pipes
IN packets are sent by the USB device controller upon IN requests from the host. All data which acknowledges or
not the bank can be read when it is empty.
The pipe must be configured first.