Datasheet

1075
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
39.5.2.14 Underflow
This error only exists for isochronous IN/OUT endpoints. It sets the Underflow Interrupt
(UOTGHS_DEVEPTISRx.UNDERFI) bit, which triggers a PEP_x interrupt if the Underflow Interrupt Enable
(UOTGHS_DEVEPTIMRx.UNDERFE) bit is one.
 An underflow can occur during the IN stage if the host attempts to read from an empty bank. A zero-length
packet is then automatically sent by the UOTGHS.
 An underflow cannot occur during the OUT stage on a CPU action, since the user may only read if the bank
is not empty (UOTGHS_DEVEPTISRx.RXOUTI is one or UOTGHS_DEVEPTISRx.RWALL is one).
 An underflow can also occur during the OUT stage if the host sends a packet while the bank is already full.
Typically, the CPU is not fast enough. The packet is lost.
 An underflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is
not full (UOTGHS_DEVEPTISRx.TXINI is one or UOTGHS_DEVEPTISRx.RWALL is one).
39.5.2.15 Overflow
This error exists for all endpoint types. It sets the Overflow interrupt (UOTGHS_DEVEPTISRx.OVERFI) bit, which
triggers a PEP_x interrupt if the Overflow Interrupt Enable (UOTGHS_DEVEPTIMRx.OVERFE) bit is one.
 An overflow can occur during the OUT stage if the host attempts to write into a bank which is too small for
the packet. The packet is acknowledged and the UOTGHS_DEVEPTISRx.RXOUTI bit is set as if no
overflow had occurred. The bank is filled with all the first bytes of the packet that fit in.
 An overflow cannot occur during the IN stage on a CPU action, since the user may only write if the bank is
not full (UOTGHS_DEVEPTISRx.TXINI is one or UOTGHS_DEVEPTISRx.RWALL is one).
39.5.2.16 HB IsoIn Error
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the micro-frame, if at least one packet has been sent to the host and less banks than expected have
been validated (by clearing the UOTGHS_DEVEPTIMRx.UOTGHS_DEVEPTIMRx.FIFOCON) for this micro-
frame, it sets the UOTGHS_DEVEPTISRx.HBISOINERRORI bit, which triggers a PEP_x interrupt if the High
Bandwidth Isochronous IN Error Interrupt Enable (HBISOINERRORE) bit is one.
For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint (NBTRANS field in
UOTGHS_DEVEPTCFGx is three (three transactions per micro-frame), only two banks are filled by the CPU
(three expected) for the current micro-frame. Then, the HBISOINERRI interrupt is generated at the end of the
micro-frame. Note that an UNDERFI interrupt is also generated (with an automatic zero-length-packet), except in
the case of a missing IN token.
39.5.2.17 HB IsoFlush
This error only exists for high-bandwidth isochronous IN endpoints.
At the end of the micro-frame, if at least one packet has been sent to the host and there is a missing IN token
during this micro-frame, the bank(s) destined to this micro-frame is/are flushed out to ensure a good data
synchronization between the host and the device.
For instance, if NBTRANS is three (three transactions per micro-frame), if only the first IN token (among 3) is well
received by the UOTGHS, then the two last banks will be discarded.
39.5.2.18 CRC Error
This error only exists for isochronous OUT endpoints. It sets the CRC Error Interrupt
(UOTGHS_DEVEPTISRx.CRCERRI) bit, which triggers a PEP_x interrupt if the CRC Error Interrupt Enable
(UOTGHS_DEVEPTIMRx.CRCERRE) bit is one.
A CRC error can occur during the OUT stage if the UOTGHS detects a corrupted received packet. The OUT
packet is stored in the bank as if no CRC error had occurred (UOTGHS_DEVEPTISRx.RXOUTI is set).