Datasheet
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1074
Figure 39-19. Example of an OUT Endpoint with one Data Bank
Figure 39-20. Example of an OUT Endpoint with two Data Banks
Detailed description
The data is read, following the next flow:
When the bank is full, UOTGHS_DEVEPTISRx.RXOUTI and UOTGHS_DEVEPTIMRx.FIFOCON are set,
which triggers a PEP_x interrupt if UOTGHS_DEVEPTIMRx.RXOUTE is one.
The user acknowledges the interrupt by writing a one to UOTGHS_DEVEPTICRx.RXOUTIC in order to clear
UOTGHS_DEVEPTISRx.RXOUTI.
The user can read the byte count of the current bank from UOTGHS_DEVEPTISRx.BYCT to know how
many bytes to read, rather than polling UOTGHS_DEVEPTISRx.RWALL.
The user reads the data from the current bank by using the USBFIFOnDATA register, until all expected data
frame is read or the bank is empty (in which case UOTGHS_DEVEPTISRx.RWALL is cleared and
UOTGHS_DEVEPTISRx.BYCT reaches zero).
The user frees the bank and switches to the next bank (if any) by clearing
UOTGHS_DEVEPTIMRx.FIFOCON.
If the endpoint uses several banks, the current one can be read while the following one is being written by the host.
Then, when the user clears UOTGHS_DEVEPTIMRx.FIFOCON, the following bank may already be read and
UOTGHS_DEVEPTISRx.RXOUTI is set immediately.
In Hi-Speed mode, the PING and NYET protocols are handled by the UOTGHS.
For a single bank, a NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the
current packet is acknowledged but there is no room for the next one.
For a double bank, the UOTGHS responds to the OUT/DATA transaction with an ACK handshake when the
endpoint accepted the data successfully and has room for another data payload (the second bank is free).
OUT
DATA
(bank 0)
ACK
UOTGHS_DEVEPTISRx.RXOUTI
UOTGHS_DEVEPTIMRx.FIFOCON
HW
OUT
DATA
(bank 0)
ACK
HW
SW
SW
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
NAK
OUT
DATA
(bank 0)
ACK
UOTGHS_DEVEPTISRx.RXOUTI
UOTGHS_DEVEPTIMRx.FIFOCON
HW
OUT
DATA
(bank 1)
ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1