Datasheet

1073
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
Figure 39-18. Abort Algorithm
39.5.2.13 Management of OUT Endpoints
Overview
OUT packets are sent by the host. All data which acknowledges or not the bank can be read when it is empty.
The endpoint must be configured first.
The UOTGHS_DEVEPTISRx.RXOUTI bit is set at the same time as UOTGHS_DEVEPTIMRx.FIFOCON when the
current bank is full. This triggers a PEP_x interrupt if the Received OUT Data Interrupt Enable
(UOTGHS_DEVEPTIMRx.RXOUTE) bit is one.
UOTGHS_DEVEPTISRx.RXOUTI shall be cleared by software (by writing a one to the Received OUT Data
Interrupt Clear (UOTGHS_DEVEPTICRx.RXOUTIC) bit to acknowledge the interrupt, which has no effect on the
endpoint FIFO.
The user then reads from the FIFO and clears the UOTGHS_DEVEPTIMRx.FIFOCON bit to free the bank. If the
OUT endpoint is composed of multiple banks, this also switches to the next bank. The
UOTGHS_DEVEPTISRx.RXOUTI and UOTGHS_DEVEPTIMRx.FIFOCON bits are updated in accordance with
the status of the next bank.
UOTGHS_DEVEPTISRx.RXOUTI shall always be cleared before clearing UOTGHS_DEVEPTIMRx.FIFOCON.
The UOTGHS_DEVEPTISRx.RWALL bit is set when the current bank is not empty, i.e. the software can read
further data from the FIFO.
Endpoint
Abort
Abort Done
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Disable the UOTGHS_DEVEPTISRx.TXINI interrupt.
UOTGHS_DEVEPT. EPRSTx = 1
UOTGHS_DEVEPTISRx.NBUSYBK
== 0?
Yes
UOTGHS_DEVEPTIDRx.TXINEC = 1
No
UOTGHS_DEVEPTIERx.KILLBKS = 1
UOTGHS_DEVEPTIMRx.KILLBK == 1?
Yes
Kill the last written bank.
Wait for the end of the
procedure
No