Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1072
Figure 39-17. Example of an IN Endpoint with 2 Data Banks
Detailed description
The data is written, following the next flow:
 When the bank is empty, UOTGHS_DEVEPTISRx.TXINI and UOTGHS_DEVEPTIMRx.FIFOCON are set,
which triggers a PEP_x interrupt if UOTGHS_DEVEPTIMRx.TXINE is one.
 The user acknowledges the interrupt by clearing UOTGHS_DEVEPTISRx.TXINI.
 The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
(USBFIFOnDATA) register, until all the data frame is written or the bank is full (in which case
UOTGHS_DEVEPTISRx.RWALL is cleared and the Byte Count (UOTGHS_DEVEPTISRx.BYCT) field
reaches the endpoint size).
 The user allows the controller to send the bank and switches to the next bank (if any) by clearing
UOTGHS_DEVEPTIMRx.FIFOCON.
If the endpoint uses several banks, the current one can be written while the previous one is being read by the host.
Then, when the user clears UOTGHS_DEVEPTIMRx.FIFOCON, the following bank may already be free and
UOTGHS_DEVEPTISRx.TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN stage of a control or
isochronous IN transaction. The Kill IN Bank (UOTGHS_DEVEPTIMRx.KILLBK) bit is used to kill the last written
bank. The best way to manage this abort is to apply the algorithm represented on Figure 39-18 on page 1073.
IN
DATA
(bank 0)
ACK
UOTGHS_DEVEPTISRx.TXINI
UOTGHS_DEVEPTIMRx.FIFOCON
write data to CPU
BANK 0
SW
SW SW
SW
IN
DATA
(bank 1)
ACK
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0