Datasheet

1071
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
Once the OUT status stage has been received, the UOTGHS waits for a SETUP request. The SETUP request has
priority over any other request and has to be ACKed. This means that any other bit should be cleared and the FIFO
reset when a SETUP is received.
The user has to consider that the byte counter is reset when a zero-length OUT packet is received.
39.5.2.12 Management of IN Endpoints
Overview
IN packets are sent by the USB device controller upon IN requests from the host. All data which acknowledges or
not the bank can be written when it is full.
The endpoint must be configured first.
The UOTGHS_DEVEPTISRx.TXINI bit is set at the same time as UOTGHS_DEVEPTIMRx.FIFOCON when the
current bank is free. This triggers a PEP_x interrupt if the Transmitted IN Data Interrupt Enable
(UOTGHS_DEVEPTIMRx.TXINE) bit is one.
UOTGHS_DEVEPTISRx.TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt
Clear bit (UOTGHS_DEVEPTIDRx.TXINIC)) to acknowledge the interrupt, what has no effect on the endpoint
FIFO.
The user then writes into the FIFO and writes a one to the FIFO Control Clear
(UOTGHS_DEVEPTIDRx.FIFOCONC) bit to clear the UOTGHS_DEVEPTIMRx.FIFOCON bit. This allows the
UOTGHS to send the data. If the IN endpoint is composed of multiple banks, this also switches to the next bank.
The UOTGHS_DEVEPTISRx.TXINI and UOTGHS_DEVEPTIMRx.FIFOCON bits are updated in accordance with
the status of the next bank.
UOTGHS_DEVEPTISRx.TXINI shall always be cleared before clearing UOTGHS_DEVEPTIMRx.FIFOCON.
The UOTGHS_DEVEPTISRx.RWALL bit is set when the current bank is not full, i.e. the software can write further
data into the FIFO.
Figure 39-16. Example of an IN Endpoint with 1 Data Bank
IN
DATA
(bank 0)
ACK
UOTGHS_DEVEPTISRx.TXINI
UOTGHS_DEVEPTIMRx.FIFOCON
HW
write data to CPU
BANK 0
SW
SW SW
SW
IN
NAK
write data to CPU
BANK 0