Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1070
Control write
Figure 39-14 on page 1070 shows a control write transaction. During the status stage, the controller will not
necessarily send a NAK on the first IN token:
 if the user knows the exact number of descriptor bytes that must be read, it can then anticipate the status
stage and send a zero-length packet after the next IN token, or
 it can read the bytes and wait for the NAKed IN Interrupt (UOTGHS_DEVEPTISRx.NAKINI), which tells that
all the bytes have been sent by the host and that the transaction is now in the status stage.
Figure 39-14. Control Write
Control read
Figure 39-15 on page 1070 shows a control read transaction. The UOTGHS has to manage the simultaneous write
requests from the CPU and the USB host.
Figure 39-15. Control Read
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all data written by the CPU is lost and clearing
UOTGHS_DEVEPTISRx.TXINI has no effect.
The user checks if the transmission or the reception is complete.
The OUT retry is always ACKed. This reception sets UOTGHS_DEVEPTISRx.RXOUTI and
UOTGHS_DEVEPTISRx.TXINI. Handle this with the following software algorithm:
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
SETUP
UOTGHS_DEVEPTISRx.RXSTPI
UOTGHS_DEVEPTISRx.RXOUTI
UOTGHS_DEVEPTISRx.TXINI
USB Bus
HW SW
OUT
HW SW
OUT
HW SW
IN IN
NAK
SW
DATA SUTATSPUTES
SETUP
UOTGHS_DEVEPTISRxRXSTPI
UOTGHS_DEVEPTISRx.RXOUTI
UOTGHS_DEVEPTISRx.TXINI
USB Bus
HW SW
IN
HW SW
IN OUT OUT
NAK
SW
SW
HW
Wr Enable
HOST
Wr Enable
CPU
DATA SUTATSPUTES