Datasheet

1069
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
 When the controller sends the upstream resume, the Upstream Resume (UOTGHS_DEVISR.UPRSM)
interrupt is set and UOTGHS_DEVISR.SUSP is cleared.
 UOTGHS_DEVCTRL.RMWKUP is cleared at the end of the upstream resume.
 If the controller detects a valid “End of Resume” signal from the host, the End of Resume
(UOTGHS_DEVISR.EORSM) interrupt is set.
39.5.2.10 STALL Request
For each endpoint, the STALL management is performed using:
 The STALL Request (UOTGHS_DEVEPTIMRx.STALLRQ) bit to initiate a STALL request.
 The STALLed Interrupt (UOTGHS_DEVEPTISRx.STALLEDI) bit, which is set when a STALL handshake has
been sent.
To answer the next request with a STALL handshake, UOTGHS_DEVEPTIMRx.STALLRQ has to be set by writing
a one to the STALL Request Set (UOTGHS_DEVEPTIERx.STALLRQS) bit. All following requests will be
discarded (UOTGHS_DEVEPTISRx.RXOUTI, etc. will not be set) and handshaked with a STALL until the
UOTGHS_DEVEPTIMRx.STALLRQ bit is cleared, which is done when a new SETUP packet is received (for
control endpoints) or when the STALL Request Clear (UOTGHS_DEVEPTIMRx.STALLRQC) bit is written to one.
Each time a STALL handshake is sent, the UOTGHS_DEVEPTISRx.STALLEDI bit is set by the UOTGHS and the
PEP_x interrupt is set.
Special considerations for control endpoints
If a SETUP packet is received into a control endpoint for which a STALL is requested, the Received SETUP
Interrupt (UOTGHS_DEVEPTISRx.RXSTPI) bit is set and UOTGHS_DEVEPTIMRx.STALLRQ and
UOTGHS_DEVEPTISRx.STALLEDI are cleared. The SETUP has to be ACKed.
This simplifies the enumeration process management. If a command is not supported or contains an error, the
user requests a STALL and can return to the main task, waiting for the next SETUP request.
STALL handshake and retry mechanism
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
UOTGHS_DEVEPTIMRx.STALLRQ bit is set and if no retry is required.
39.5.2.11 Management of Control Endpoints
Overview
A SETUP request is always ACKed. When a new SETUP packet is received, the
UOTGHS_DEVEPTISRx.RXSTPI is set; the Received OUT Data Interrupt (UOTGHS_DEVEPTISRx.RXOUTI) bit
is not.
The FIFO Control (UOTGHS_DEVEPTIMRx.FIFOCON) bit and the Read-write Allowed
(UOTGHS_DEVEPTISRx.RWALL) bit are irrelevant for control endpoints. The user shall never use them on these
endpoints. When read, their values are always zero.
Control endpoints are managed using:
 the UOTGHS_DEVEPTISRx.RXSTPI bit, which is set when a new SETUP packet is received and which
shall be cleared by firmware to acknowledge the packet and to free the bank;
 the UOTGHS_DEVEPTISRx.RXOUTI bit, which is set when a new OUT packet is received and which shall
be cleared by firmware to acknowledge the packet and to free the bank;
 the Transmitted IN Data Interrupt (UOTGHS_DEVEPTISRx.TXINI) bit, which is set when the current bank is
ready to accept a new IN packet and which shall be cleared by firmware to send the packet.