Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1066
Figure 39-12. Device Mode States
After a hardware reset, the UOTGHS device mode is in Reset state. In this state:
 the macro clock is stopped to minimize the power consumption (UOTGHS_CTRL.FRZCLK is written to one),
 the internal registers of the device mode are reset,
 the endpoint banks are de-allocated,
 neither D+ nor D- is pulled up (UOTGHS_DEVCTRL.DETACH is written to one).
D+ or D- will be pulled up according to the selected speed as soon as the UOTGHS_DEVCTRL.DETACH bit is
written to zero and VBus is present. See “Device mode” for further details.
When the UOTGHS is enabled (UOTGHS_CTRL.USBE is written to one) in device mode (UOTGHS_SR.ID is
one), its device mode state goes to the Idle state with minimal power consumption. This does not require the USB
clock to be activated.
The UOTGHS device mode can be disabled and reset at any time by disabling the UOTGHS (by writing a zero to
UOTGHS_CTRL.USBE) or when the host mode is engaged (UOTGHS_SR.ID is zero).
39.5.2.3 USB Reset
The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the controller:
 All endpoints are disabled, except the default control endpoint.
 The default control endpoint is reset (see Section 39.5.2.4 for more details).
 The data toggle sequence of the default control endpoint is cleared.
 At the end of the reset process, the End of Reset (UOTGHS_DEVISR.EORST) bit is set.
 During a reset, the UOTGHS automatically switches to the Hi-Speed mode if the host is Hi-Speed capable
(the reset is called Hi-Speed reset). The user should observe the UOTGHS_SR.SPEED field to know the
speed running at the end of the reset (UOTGHS_DEVISR.EORST is one).
Reset
Idle
HW
UOTGHS_CTRL.USBE = 0
| UOTGHS_SR.ID = 0
<any
other
state>
UOTGHS_CTRL.USBE = 0
| UOTGHS_SR.ID = 0
& UOTGHS_SR.ID = 1
UOTGHS_CTRL.USBE = 1
UOTGHS_HSTCTRL.RESET