Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1062
Figure 39-7 on page 1062 illustrates the allocation and reorganization of the DPRAM in a typical example.
Figure 39-7. Allocation and Reorganization of the DPRAM
1. The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order. Each pipe/endpoint
then owns a memory area in the DPRAM.
2. The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller.
3. In order to free its memory, its UOTGHS_DEVEPTCFGx.ALLOC bit is written to zero. The pipe/endpoint 4
memory window slides down, but the pipe/endpoint 5 does not move.
4. If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller allocates a memory
area after the pipe/endpoint 2 memory area and automatically slides up the pipe/endpoint 4 memory window.
The pipe/endpoint 5 does not move and a memory conflict appears as the memory windows of the
pipes/endpoints 4 and 5 overlap. The data of these pipes/endpoints is potentially lost.
Note:
2. There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as the memory allocation
and de-allocation may affect only higher pipes/endpoints.
3. Deactivating then reactivating the same pipe/endpoint with the same configuration only modifies temporarily the
controller DPRAM pointer and size for this pipe/endpoint. Nothing changes in the DPRAM, higher endpoints seem
not to have been moved and their data is preserved as far as nothing has been written or received into them while
changing the allocation state of the first pipe/endpoint.
4. When the user writes a one to the UOTGHS_DEVEPTCFGx.ALLOC bit, the Configuration OK Status bit
(UOTGHS_DEVEPTISRx.CFGOK) is set only if the configured size and number of banks are correct as
compared to the endpoint maximal allowed values and to the maximal FIFO size (i.e. the DPRAM size). The
UOTGHS_DEVEPTISRx.CFGOK value does not consider memory allocation conflicts.
39.5.1.7 Pad Suspend
Figure 39-8 on page 1063 shows the pad behavior.
Free Memory
PEP0
PEP1
PEP2
PEP3
PEP4
PEP5
Free Memory
PEP0
PEP1
PEP2
PEP4
PEP5
Free Memory
PEP0
PEP1
PEP2
PEP4
PEP5
Pipe/Endpoint 3
Disabled
Pipe/Endpoint 3
Memory Freed
Free Memory
PEP0
PEP1
PEP2
PEP3 (larger size)
PEP5
Pipe/Endpoint 3
Activated
PEP4 Lost Memory
PEP4
Conflict
PEP3
(ALLOC stays at 1)
Pipes/Endpoints 0..5
Activated
Device:
UOTGHS_DEVEPT.EPENx = 1
UOTGHS_DEVEPTCFGx.ALLOC = 1
Host:
UOTGHS_HSTPIP.EPENx = 1
UOTGHS_HSTPIPCFGx.ALLOC = 1
Device:
UOTGHS_DEVEPT.EPEN3 = 0
Host:
UOTGHS_HSTPIP.EPEN3 = 0
Device:
UOTGHS_DEVEPTCFG3.ALLOC = 0
Host:
UOTGHS_HSTPIPCFG3.ALLOC = 0
Device:
UOTGHS_DEVEPT.EPEN3 = 1
UOTGHS_DEVEPTCFG3.ALLOC = 1
Host:
UOTGHS_HSTPIP.EPEN3 = 1
UOTGHS_HSTPIPCFG3.ALLOC = 1