Datasheet

1059
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
The UOTGHS can be disabled at any time by writing a zero to UOTGHS_CTRL.USBE. In fact, writing a zero to
UOTGHS_CTRL.USBE acts as a hardware reset, except that the UOTGHS_CTRL.OTGPADE,
UOTGHS_CTRL.VBUSPO, UOTGHS_CTRL.FRZCLK, UOTGHS_CTRL.UIDE, UOTGHS_CTRL.UIMOD and,
UOTGHS_DEVCTRL.LS bits are not reset.
39.5.1.3 Interrupts
One interrupt vector is assigned to the USB interface. Figure 39-6 on page 1059 shows the structure of the USB
interrupt system.
Figure 39-6. Interrupt System
See Section 39.5.2.19 and Section 39.5.3.13 for further details about device and host interrupts.
UOTGHS_CTRL.IDTE
UOTGHS_SR.IDTI
UOTGHS_SR.VBUSTI
UOTGHS_CTRL.VBUSTE
UOTGHS_SR.SRPI
UOTGHS_CTRL.SRPE
UOTGHS_SR.VBERRI
UOTGHS_CTRL.VBERRE
UOTGHS_SR.BCERRI
UOTGHS_CTRL.BCERRE
UOTGHS_SR.ROLEEXI
UOTGHS_CTRL.ROLEEXE
UOTGHS_SR.HNPERRI
UOTGHS_CTRL.HNPERRE
UOTGHS_SR.STOI
UOTGHS_CTRL.STOE
USB General
Interrupt
USB Device
Interrupt
USB Host
Interrupt
USB
Interrupt
Asynchronous interrupt source
UOTGHS_DEVIMR.SUSPE
UOTGHS_DEVIMR.SUSP
UOTGHS_DEVIMR.SOF
UOTGHS_DEVIMR.SOFE
UOTGHS_DEVIMR.EORST
UOTGHS_DEVIMR.EORSTE
UOTGHS_DEVIMR.WAKEUP
UOTGHS_DEVIMR.WAKEUPE
UOTGHS_DEVIMR.EORSM
UOTGHS_DEVIMR.EORSME
UOTGHS_DEVIMR.UPRSM
UOTGHS_DEVIMR.UPRSME
UOTGHS_DEVIMR.EPXINT
UOTGHS_DEVIMR.EPXINTE
UOTGHS_DEVIMR.DMAXINT
UOTGHS_DEVIMR.DMAXINTE
UOTGHS_HSTIMR.DCONNIE
UOTGHS_HSTISR.DCONNI
UOTGHS_HSTISR.DDISCI
UOTGHS_HSTIMR.DDISCIE
UOTGHS_HSTISR.RSTI
UOTGHS_HSTIMR.RSTIE
UOTGHS_HSTISR.RSMEDI
UOTGHS_HSTIMR.RSMEDIE
UOTGHS_HSTISR.RXRSMI
UOTGHS_HSTIMR.RXRSMIE
UOTGHS_HSTISR.HSOFI
UOTGHS_HSTIMR.HSOFIE
UOTGHS_HSTISR.HWUPI
UOTGHS_HSTIMR.HWUPIE
UOTGHS_HSTISR.PXINT
UOTGHS_HSTIMR.PXINTE
UOTGHS_HSTISR.DMAXINT
UOTGHS_HSTIMR.DMAXINTE
UOTGHS_DEVEPTIMRx.TXINE
UOTGHS_DEVEPTISRx.TXINI
UOTGHS_DEVEPTISRx.RXOUTI
UOTGHS_DEVEPTIMRx.RXOUTE
UOTGHS_DEVEPTISRx.RXSTPI
UOTGHS_DEVEPTIMRx.RXSTPE
UOTGHS_DEVEPTISRx.UNDERFI
UOTGHS_DEVEPTIMRx.UNDERFE
UOTGHS_DEVEPTISRx.NAKOUTI
UOTGHS_DEVEPTIMRx.NAKOUTE
UOTGHS_DEVEPTISRx.NAKINI
UOTGHS_DEVEPTIMRx.NAKINE
UOTGHS_DEVEPTISRx.OVERFI
UOTGHS_DEVEPTIMRx.OVERFE
UOTGHS_DEVEPTISRx.STALLEDI
UOTGHS_DEVEPTIMRx.STALLEDE
UOTGHS_DEVEPTISRx.CRCERRI
UOTGHS_DEVEPTIMRx.CRCERRE
UOTGHS_DEVEPTISRx.SHORTPACKET
UOTGHS_DEVEPTIMRx.SHORTPACKETE
UOTGHS_DEVEPTISRx.DTSEQ=MDATA & UESTAX.RXOUTI
UOTGHS_DEVEPTIMRx.MDATAE
UOTGHS_HSTPIPIMRx.RXINE
UOTGHS_HSTPIPISRx.RXINI
UOTGHS_HSTPIPISRx.TXOUTI
UOTGHS_HSTPIPIMRx.TXOUTE
UOTGHS_HSTPIPISRx.TXSTPI
UOTGHS_HSTPIPIMRx.TXSTPE
UOTGHS_HSTPIPISRx.UNDERFI
UOTGHS_HSTPIPIMRx.UNDERFIE
UOTGHS_HSTPIPISRx.PERRI
UOTGHS_HSTPIPIMRx.PERRE
UOTGHS_HSTPIPISRx.NAKEDI
UOTGHS_HSTPIPIMRx.NAKEDE
UOTGHS_HSTPIPISRx.OVERFI
UOTGHS_HSTPIPIMRx.OVERFIE
UOTGHS_HSTPIPISRx.RXSTALLDI
UOTGHS_HSTPIPIMRx.RXSTALLDE
UOTGHS_HSTPIPISRx.CRCERRI
UOTGHS_HSTPIPIMRx.CRCERRE
UOTGHS_HSTPIPISRx.SHORTPACKETI
UOTGHS_HSTPIPIMRx.SHORTPACKETIE
UOTGHS_HSTPIPISRx.NBUSYBK
UOTGHS_HSTPIPIMRx.NBUSYBKE
UDDMAX_CONTROL.EOT_IRQ_EN
UOTGHS_DEVDMASTATUSx.EOT_STA
UOTGHS_DEVDMASTATUSx.EOCH_BUFF_STA
UDDMAX_CONTROL.EOBUFF_IRQ_EN
UOTGHS_DEVDMASTATUSx.DESC_LD_STA
UDDMAX_CONTROL.DESC_LD_IRQ_EN
UOTGHS_HSTDMACONTROLx.EOT_IRQ_EN
UOTGHS_HSTDMASTATUSx.EOT_STA
UOTGHS_HSTDMASTATUSx.EOCH_BUFF_STA
UOTGHS_HSTDMACONTROLx.EOBUFF_IRQ_EN
UOTGHS_HSTDMASTATUSx.DESC_LD_STA
UOTGHS_HSTDMACONTROLx.DESC_LD_IRQ_EN
USB Device
Endpoint X
Interrupt
USB Host
Pipe X
Interrupt
USB Device
DMA Channel X
Interrupt
USB Host
DMA Channel X
Interrupt
UOTGHS_DEVIMR.MSOFE
UOTGHS_DEVIMR.MSOF
UOTGHS_DEVEPTISRx.HBISOINERRI
UOTGHS_DEVEPTIMRx.HBISOINERRE
UOTGHS_DEVEPTISRx.HBISOFLUSHI
UOTGHS_DEVEPTIMRx.HBISOFLUSHE
UOTGHS_DEVEPTISRx.DTSEQ=DATAX & UESTAX.RXOUTI
UOTGHS_DEVEPTIMRx.DATAXE
UOTGHS_DEVEPTISRx.TRANSERR
UOTGHS_DEVEPTIMRx.TRANSERRE
UOTGHS_DEVEPTISRx.NBUSYBK
UOTGHS_DEVEPTIMRx.NBUSYBKE