Datasheet

1057
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
39.4 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described below.
39.4.1 I/O Lines
The UOTGVBOF and UOTGID pins are multiplexed with I/O Controller lines and may also be multiplexed with
lines of other peripherals. In order to use them with the USB, the user must first configure the I/O Controller to
assign them to their USB peripheral functions.
 If UOTGID is used, the I/O Controller must be configured to enable the internal pull-up resistor of its pin.
 If UOTGVBOF or UOTGID is not used by the application, the corresponding pin can be used for other
purposes by the I/O Controller or by other peripherals.
39.4.2 Clocks
The clock for the UOTGHS bus interface is generated by the Power Management Controller. This clock can be
enabled or disabled in the Power Management Controller. It is recommended to disable the UOTGHS before
disabling the clock, to avoid freezing the UOTGHS in an undefined state.
The UOTGHS can work in two different modes:
 Normal mode (SPDCONF =1) where High speed, Full speed and Low speed are available.
 Low-power mode (SPDCONF =0) where Full speed and Low speed are available.
For normal mode:
1. Enable the UPLL 480MHz
2. Wait for the UPLL 480 MHz to be considered as locked by the PMC
3. Enable the UOTGHS Peripheral clock (PMC_PCER)
4. The UOTGHS will use USB_480 M clock (refer to the PMC).
For low-power mode:
1. As USB_48M must be set to 48 MHz (refer to the PMC), select either the PLLA or the UPLL (previously
set to ON), and program the PMC_USB register (source selection and divider)
2. Enable the UOTGCK bit (PMC_SCER)
3. Enable the UOTGHS Peripheral clock (PMC_PCER)
4. Put the UOTGHS in Low power mode (SPDCONF)
39.4.3 Interrupts
The UOTGHS interrupt request line is connected to the interrupt controller. Using the UOTGHS interrupt requires
the interrupt controller to be programmed first.
39.4.4 USB Pipe/Endpoint x FIFO Data Register (USBFIFOxDATA)
The application has access to each Pipe/Endpoint FIFO through its reserved 32 KB address space. The
application can access a 64 KB buffer linearly or fixedly as the DPRAM address increment is fully handled by
hardware. Byte, half-word and word access are supported. Data should be accessed in a big-endian way.
Disabling the UOTGHS (by writing a zero to the UOTGHS_CTRL.USBE bit) does not reset the DPRAM.
Table 39-3. I/O Lines
Instance Signal I/O Line Peripheral
UOTGHS UOTGID PB11 A
UOTGHS UOTGVBOF PB10 A