Datasheet

1045
SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
• CES: Counter Event Selection
The bit CES defines when the channel counter event occurs when the period is center aligned (flag CHIDx in the “PWM
Interrupt Status Register 1” on page 1013).
CALG = 0 (Left Alignment):
0/1 = The channel counter event occurs at the end of the PWM period.
CALG = 1 (Center Alignment):
0 = The channel counter event occurs at the end of the PWM period.
1 = The channel counter event occurs at the end of the PWM period and at half the PWM period.
• DTE: Dead-Time Generator Enable
0 = The dead-time generator is disabled.
1 = The dead-time generator is enabled.
• DTHI: Dead-Time PWMHx Output Inverted
0 = The dead-time PWMHx output is not inverted.
1 = The dead-time PWMHx output is inverted.
• DTLI: Dead-Time PWMLx Output Inverted
0 = The dead-time PWMLx output is not inverted.
1 = The dead-time PWMLx output is inverted.