Datasheet

SAM3X / SAM3A [DATASHEET]
Atmel-11057C-ATARM-SAM3X-SAM3A-Datasheet_23-Mar-15
1044
38.7.37 PWM Channel Mode Register
Name: PWM_CMRx [x=0..7]
Address: 0x40094200 [0], 0x40094220 [1], 0x40094240 [2], 0x40094260 [3], 0x40094280 [4], 0x400942A0 [5],
0x400942C0 [6], 0x400942E0 [7]
Access: Read-write
This register can only be written if the bits WPSWS2 and WPHWS2 are cleared in “PWM Write Protect Status Register” on
page 1039.
• CPRE: Channel Pre-scaler
• CALG: Channel Alignment
0 = The period is left aligned.
1 = The period is center aligned.
• CPOL: Channel Polarity
0 = The OCx output waveform (output from the comparator) starts at a low level.
1 = The OCx output waveform (output from the comparator) starts at a high level.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––DTLIDTHIDTE
15 14 13 12 11 10 9 8
–––––CESCPOLCALG
76543210
–––– CPRE
Value Name Description
0b0000 MCK Master clock
0b0001 MCK_DIV_2 Master clock/2
0b0010 MCK_DIV_4 Master clock/4
0b0011 MCK_DIV_8 Master clock/8
0b0100 MCK_DIV_16 Master clock/16
0b0101 MCK_DIV_32 Master clock/32
0b0110 MCK_DIV_64 Master clock/64
0b0111 MCK_DIV_128 Master clock/128
0b1000 MCK_DIV_256 Master clock/256
0b1001 MCK_DIV_512 Master clock/512
0b1010 MCK_DIV_1024 Master clock/1024
0b1011 CLKA Clock A
0b1100 CLKB Clock B